1. Field of the Invention
The present invention relates to a semiconductor memory having a redundancy function whereby defective elements are replaced by redundant elements, thereby improving the production yield, and more particularly to a semiconductor memory that uses an electrically programmable nonvolatile semiconductor memory as a redundant-address storing memory for storing the address of a replaced element.
2. Description of the Prior Art
Semiconductor memories are not allowed to contain even a single defect in their memory cell arrays, and if a defect is present in any one of the memory cells, the semiconductor memory is rendered defective. However, as the capacity of semiconductor memory increases, it is becoming increasingly difficult to fabricate memory cell arrays that contain no defective bits. In particular, in the case of semiconductor memories developed using new manufacturing technologies, the problem is that the defect rate tends to be high and the yield tends to be extremely low in the initial period of mass production.
Redundant circuit techniques are used to overcome this problem.
Semiconductor memories using redundant circuit techniques contain redundant memory cells, in addition to the normal memory cell arrays consisting of normal cells, that are brought into use to replace defective normal cells, and a redundancy decision circuit that performs control so that, when access is attempted to a defective normal cell, the access is actually made to the redundant memory cell. The redundancy decision circuit is required to detect any attempted access to defective normal cells. For this purpose, the redundancy decision circuit of the prior art includes a fuse ROM for storing the addresses of replaced elements and a match detection circuit for detecting whether the input address signal matches the address of a replaced element. In the following, the address stored in the fuse ROM is called the redundant address. The match detection circuit is usually constructed with exclusive NOR gates, the number of which is equal to the number of address bits used to access the replaced element, and a multiple-input AND or NAND gate to which the outputs of the exclusive NOR gates are input. Furthermore, when no normal cells are defective and the redundancy mechanism is not switched on, it is not necessary to select a redundant cell even if the input address matches the redundant address. For this purpose, the redundancy decision circuit further includes a redundancy memory circuit for storing information regarding whether the redundancy function has been switched on. This redundancy memory circuit is usually constructed with a fuse ROM. When the redundancy function is switched on, if the address signal matches, selection of the normal cell is disabled by the output of the redundancy memory circuit; on the other hand, when the redundancy is not switched on, the normal cell is selected for access while disabling access to the redundant memory cell even if the address signal matches.
While the prior art redundancy decision circuit using the fuse ROMs, as described above, has the advantage that the area that the redundancy decision circuit takes up is small, the prior art configuration involves a cumbersome procedure in fabrication, requiring removal of the wafer from die sorting equipment that holds the wafer in place, blowing the fuses using a laser cutting device, and then retesting the completed circuit. This presents a problem in that polysilicon particles generated by the laser cutting device may adversely affect other circuit elements.
To avoid this problem, there is proposed a semiconductor memory which uses an EPROM, instead of the fuse ROM, for storing a redundant address. Writing to an EPROM requires the application of a higher-than-normal voltage to the EPROM gate, and the power supply circuit has a switching function for switching to the appropriate supply voltage. The semiconductor memory using an EPROM for storing a redundant address uses the same match detection circuit as described above, consisting of a plurality of exclusive NOR gates and an AND or NAND gate, to detect whether the input address signal matches the stored address.
In the fabrication of a semiconductor memory that uses EPROMs for the redundant-address detection circuit and redundancy memory circuit, a processing step is required for forming the EPROMs; at this time, this configuration is employed for memories whose normal memory cells are fabricated using EPROM, EEPROM, or flash memory technology. Using EPROMs for the redundant-address detection and redundancy memory circuits requires a write circuit for writing a redundant address to the EPROMs of the redundancy decision circuit, and therefore has the problem of increasing the size and complexity of the entire circuit. On the other hand, compared with the configuration using fuse ROMs, the configuration using EPROMs has the advantages that the redundancy can be built in and retesting can be carried out while, at the same time, conducting die sorting, and that the process does not generate polysilicon particles that could adversely affect other circuit elements.
The prior art semiconductor memories having redundant circuits described above have the problem that the circuit size is increased when the circuit comprising exclusive NOR gates is used for identifying a redundant address. A further problem is that the access speed to a redundant cell is slower compared to the access speed to a normal cell since the access needs to be processed not only through the redundant-address detection circuit but through further gates before being combining with the output of the redundancy memory circuit that stores information as to whether the redundant cell is to be used. The operating speed of a semiconductor memory is defined on the basis of the slowest access speed. In the above case, the access speed to the redundant cell determines the operating speed of the memory. The recent trend to higher microprocessor speeds requires increasing the operating speeds of semiconductor memories, and it is desirable that the memory have the highest possible speed.
Furthermore, with the recent trend to decreased operating voltages for electronic appliances, semiconductor memories are being designed to operate on lower voltages than before. Semiconductor memories, such as EPROMs, EEPROMs, and flash memories, require the application of a higher gate voltage when writing than when reading, but even in the case of these semiconductor memories that require two different voltages, the memories are being designed for use with a single power supply to reduce the load on electronic appliances.
For semiconductor memories designed for use with a single low-voltage power supply, using EPROMs, etc. for storing redundant addresses gives rise to a problem as to how the redundant addresses should be written.
In the case of EPROMs, EEPROMs, and flash memories that are designed for use with a single low-voltage, power supply, the write voltage needs to be boosted internally, but since the provision of a booster circuit takes up chip area, the booster circuit must be designed to have just enough capacity for writing to the normal cells if the chip area is to be reduced. Large-capacity semiconductor memories, however, require eight or more bits for each of the row and column addresses. The problem here is that the redundant-address bits cannot be written using a low capacity internal booster circuit.